The present invention relates to a method for fabricating a semiconductor device, more specifically a method for fabricating a semiconductor device having an insulation film.
In a conventional method for fabricating a semiconductor device, an inter-layer insulation film is formed by, e.g., BPSG on a semiconductor substrate with a gate electrode, an interconnection layer, etc. formed on, and then the surface of the inter-layer insulation film is planarized by long-time and high-temperature reflow process.
On the other hand, recently the technique of forming a metal silicide layer on the surface of the source/drain-diffused layer of a transistor is noted. Cobalt silicide is noted as the metal silicide. This technique can decrease the contact resistance of the source/drain.
However, it is not desirable to make the surface of the inter-layer insulation film planarized by the reflow process in forming a metal silicide layer on the surface of the source/drain diffused layer. The reflow process for planarizing the surface of the inter-layer insulation film is performed at high temperatures as high as 800–1000° C. and furthermore for a long period of time, which makes the silicidation excessive. The excessive silicidation is a cause for a short, etc.
Then, a technique that the inter-layer insulation film deposited in a state where a pressure in a deposition chamber is set to be a little lower than the atmospheric pressure, i.e., to be the sub-atmospheric pressure, and then the inter-layer insulation film is further deposited in a state where a pressure in the deposition chamber is set low is proposed (refer to Patent Reference 1).
In depositing the inter-layer insulation film in a state where a pressure in the deposition chamber is set to be a first pressure which is a little lower than the atmospheric pressure, the inter-layer insulation film is deposited at a relatively low film deposition rate but can be buried without failure in-between the gate electrode, etc. The inter-layer insulation film can be deposited at a high film deposition rate in depositing the inter-layer insulation film in a state where a pressure in the deposition chamber is set to be a second pressure which is lower. The proposed method for fabricating a semiconductor device can form the inter-layer insulation film which is to some extent flat without using the reflow.
Following references disclose the background art of the present invention.
[Patent Reference 1]
Specification of Japanese Patent Application Unexamined Publication No. 2001-338976
[Patent Reference 2]
Specification of Japanese Patent Application Unexamined Publication No. Hei 6-140572
[Patent Reference 3]
Specification of Japanese Patent Application Unexamined Publication No. Hei 7-111253
[Patent Reference 4]
Specification of Japanese Patent Application Unexamined Publication No. 2001-244264
However, the proposed method for fabricating the semiconductor device cannot obtain the inter-layer insulation film with a sufficiently flat surface.